1. Field of the Invention
The present invention relates generally to an integrated, space efficient multi-level semiconductor chip scale package and, more particularly, to a high capacity memory semiconductor package using a minimum number of solder ball arrays for board level interconnection.
2. Background Art
Chip scale packages (CSP) are now used in many high-density dual-inline memory modules (DIMM) for both high electrical performance and for space conservation, because the package sizes are typically no more than 20% larger than the size of the bare die. Compared to other types of semiconductor packages such as lead frame type thin small outline. packages (TSOP) or ball grid array (BGA) packages, CSP packages are substantially smaller in size such that a larger number of the memory packages can be placed on a DIMM module to achieve more memory capacity.
When a typical monolithic placement of semiconductor packages occupies all the available space on the printed wiring board (PWB) used in a DIMM module, a common way to increase the memory density is by using vertically stacked packages such as those described in U.S. Pat. No. 6,404,662 issued Jun. 11, 2002, wherein a stacked memory package is shown for a Rambus memory package. A very thin multi-chip package assembly is disclosed in U.S. Pat. No. 6,239,496 issued May 29, 2001. In U.S. Pat. No. 6,455,928, issued Sep. 24, 2002, a multiple stackable fine ball grid array (FBGA) assembly is described. In such stackable assemblies, identical FBGA packages are usually vertically stacked by placing one package on top of the other in the manner shown in FIG. 1 of the drawings.
The stacked packages 10-1 and 10-2 shown in the assembly of FIG. 1 include a number (e.g. two) of integrated circuit (IC) chips 1 that are located one above the other. The IC chip 1 from each stacked package 10-1 and 10-2 is bonded to a substrate 3 by means of a die attach adhesive 5. Each substrate 3 is laid over a substrate metalization circuit 7, and each metalization circuit 7 is supported upon an array of electrically conductive solder balls 9 that run along the outer perimeter of the package. The solder balls 9 that are associated with the upper IC chip package 10-1 are electrically connected to the solder balls 9 that are associated with the lower IC package 10-2 at respective electrical pads 14 that are connected together through the lower level substrate 3. Thus, it may be appreciated that the upper and lower level packages 10-1 and 10-2 that carry respective IC chips 1 are separated from one another by the solder balls 9. A gold bond wire 11 projects from a downwardly facing input/output pad 13 on each IC chip 1 for attachment to the substrate metalization circuit 7 via an opening that is formed in the substrate 3 of the upper and lower level packages 10-1 and 10-2. The gold bond wires 11 are surrounded by a suitable protective encapsulant 15.
Consequently, the height of the stacked package assembly of FIG. 1 is the same as the combined height of the individual IC chip packages 10-1 and 10-2. Furthermore, by using an array of solder balls 9 on each individual package 10-1 and 10-2 for the package-to-package electrical interconnection, the solder ball height, which typically is greater in thickness than the semiconductor chip 1 and its supporting substrate, will cause a gap 16 to be established between the upper and lower IC chip packages 10-1 and 10-2 in a vertical stack, unless a space-filling material is used between the adjacent stacked packages. Without using such a space-filling material, the stacked packages 10-1 and 10-2 can have a weak structural integrity since it is only the solder balls 9 along the outer perimeter of the assembly that are interconnected and the thin, fragile IC chips 1 are cantilevered or even partially suspended between the solder ball arrays.
A further deficiency in the perimeter-solder ball interconnection shown in FIG. 1 is that the overall size of the package must be increased to accommodate the relatively large solder balls 9 located along the perimeter. Hence, the stacked package assembly of FIG. 1 is larger in size than an equivalent single-chip CSP package 10-1 or 10-2 having a solder ball array located directly underneath the IC chip. This size increase reduces the effectiveness of the stacked package assembly as a compact chip scale package. Therefore, there is a need for a stacked package assembly that does not increase the planar area (in the x-y dimension) compared to the single-chip packages of the assembly having solder balls attached directly underneath the IC chip. That is to say, it is desirable to have a multi-level stacked package assembly that will only increase slightly the area occupied by an equivalent single-chip package. The stacked package assembly must also have strong structural integrity for handling, assembly and long-term reliability.
In this same regard, applications in portable electronics devices continue to require that the IC chip packages be thinner, lighter, and more robust in structure. Therefore, there is a need to provide an improved structurally robust, low profile, high density, stacked CSP package for DRAM memory and other applications. The improved package should have lower overall profile (height) and more robustness and rigidity compared to a typical stackable CSP assembly having perimeter solder ball interconnections lying between individual vertically stacked, single-chip packages as shown in FIG. 1. For maximum flexibility, the single-chip package prior to assembly should have the option of being used individually as a stand alone, single-chip package for monolithic board assembly. Or, when desired, the stand alone single-chip packages should be capable of being assembled together to form a vertically integrated multi-level chip scale package with essentially the same footprint as the single-chip package prior to stacking. Furthermore, the total height of the integrated package assembly should be less than the sum of the individual packages when stacked together using their respectively attached solder ball arrays.
In general terms, a vertically integrated multi-chip CSP package is assembled by stacking two or more single-chip CSP subassemblies one above the other. The assembly perimeter is then encapsulated with an encapsulant material such that the finished stacked package assembly has the appearance of a single CSP package having the same array of interconnection solder balls for board level assembly to a printed wiring board (PWB). The upper and the lower level CSP package subassemblies are bonded together by using conventional die attach adhesive materials. In one embodiment having a two-chip package stack, both the upper and the lower level package subassemblies are single-chip memory ball grid arrays (mBGA), i.e., a CSP package characterized by center pad bonding in a face-down configuration and adapted for use in a DRAM memory module.
More particularly, substantially identical upper and lower stand-alone CSP package subassemblies are stacked one above the other to form a space efficient integrated two package stacked assembly. Each of the upper and lower stand-alone package subassemblies includes a single integrated circuit chip that is bonded to a thin substrate. The input/output pads located below the chip are electrically connected to wire bond pads on the substrate by means of gold wires. The wire bond pads on the substrate are encapsulated by a protective encapsulant. Perimeter wire bonding pads are located on the top of the substrate and solder ball bonding pads are located on the bottom of the substrate. The perimeter wire bonding pads and the solder ball bonding pads located on opposite sides of the substrate are electrically connected together through the substrate. An array of solder balls is attached along the bottom of the substrate at the solder ball bonding pads thereof. The upper and lower level CSP package subassemblies of the two package stacked assembly differ from one another in that the substrate of the lower level subassembly and the perimeter wire bonding pads on the lower level substrate are slightly longer than the substrate of the upper level subassembly and the wire bonding pads thereon. This difference in length is necessary for a wire bond machine to perform vertical wire bonding between the upper and lower wire bonding pads of the upper and lower level CSP package subassemblies.
The upper level CSP package subassembly is mounted on and adhesively bonded to the lower level package subassembly, but without any solder balls located therebetween. Thus, an integrated stacked package is formed with the upper and lower CSP package subassemblies stacked directly one above the other. The stacked CSP package subassemblies are wire bonded by attaching gold wires between the perimeter wire bonding pads on the substrates of the upper and lower CSP package subassemblies. An encapsulant is then applied to the entire stacked assembly to seal off the wires to reinforce the adhesive bond between the upper and lower level package subassemblies. In the completed stacked assembly, only a single array of solder balls is attached along the bottom of the substrate of the lower level CSP package subassembly.
Although the preferred stacked assembly has a pair of CSP package subassemblies stacked one above the other, any suitable number (e.g. four) of CSP package subassemblies may be otherwise integrated in a vertical stack according to the teachings of this invention. Accordingly, an integrated package assembly is now possible comprising a plurality of identical integrated circuit chips that are stacked one above the other without taking up additional space on a PWB so as to be ideally suited for use in a high capacity DRAM memory module.